A new research framework called GoalEvolve teaches AI systems to fix chip design flaws by pinpointing which stage of a multi-step process is actually causing the problem.
Physical chip design runs through multiple linked stages, and a fix that helps one stage can quietly wreck the next one. GoalEvolve tackles that by converting unmet performance targets into measurable gaps, then using stage-by-stage checkpoint data to find the specific stage responsible for a bottleneck. An LLM teacher model narrows down which algorithmic decision to target, while multiple student agents test and validate proposed fixes across the full design flow. In tests on eight ASAP7 chip designs, the system improved post-route timing slack by 30.67% on average and cut leakage and dynamic power by 21.18% and 9.42%, compared to a default OpenROAD baseline.
Most AI-driven chip design tools optimize whatever metric is easiest to measure at each stage, which can produce results that look good locally and fall apart once the full flow runs. By tying every evolutionary step back to the final quality-of-result target, GoalEvolve makes a case that stage-blindness, not model capability, has been the real bottleneck in automated chip design tools.
Those gains are still measured against academic baselines and a fixed benchmark suite, not the sprawling, proprietary flows commercial EDA vendors actually sell. The framework partially closes the gap with commercial-tool goals on some designs and beats them on others, so the real test is whether it holds up once someone points it at a production-grade chip.