A team of researchers has built an AI agent that argues with itself to make computer chips faster and smaller.
The system, called SKILL, coordinates three large language models: GPT-4o handles strategic planning, Claude Sonnet 4 does detailed reasoning, and Gemini 2.5 Pro handles quick analysis. A reinforcement learning agent trained with PPO works alongside them, directly interacting with logic synthesis tools to learn what actually works. A built-in self-correcting module watches power, delay, and area metrics as the system runs, and calls in the LLMs to fix course when the agent's choices go sideways. Tested on the IWLS, OpenCores, and EPFL benchmark suites, SKILL beat expert-designed synthesis flows by 12.4 percent on power-delay-area metrics and succeeded 86.3 percent of the time on chips with up to 500,000 logic gates.
Logic synthesis optimization is the unglamorous, expensive part of chip design: turning a circuit description into an efficient physical layout, a search problem so vast that engineers have long leaned on rigid, hand-built flows or reinforcement learning that eats enormous amounts of compute for marginal gains. SKILL's pitch is that LLMs can supply judgment and interpretability that pure RL lacks, while RL supplies the ability to actually learn from the tool's feedback rather than just reason about it in the abstract.
That combination, language models steering while reinforcement learning does the legwork, is becoming a common template well beyond chip design. This paper is really about where the actual gains are showing up: hooking an LLM to a domain-specific feedback loop, not just handing it a clever prompt.