IBM says it has built chip technology that performs like a sub-1 nanometer design - even though no such chip physically exists yet.
The new "nanostack" architecture can pack nearly 100 billion transistors onto a chip the size of a fingernail, roughly double the density of IBM's previous generation. IBM is pitching it at AI data centers, where compute density and energy efficiency are the two levers everyone is fighting over. Jay Gambetta, director of IBM Research, called it "a meaningful leap forward" and said it points toward computing power growing without a matching rise in energy draw.
The number matters less than the asterisk attached to it. Building physical features smaller than 1 nanometer runs into hard quantum limits - electrons start tunneling where they shouldn't, and reliability collapses. IBM is not claiming it solved that problem. It is claiming its nanostack architecture delivers performance equivalent to what a sub-1nm chip would theoretically provide. That reframe is doing a lot of work in the headline.
The chip industry has been playing loose with node naming for years - "5nm" and "3nm" chips from TSMC and Intel do not have features that small either. IBM is at least being clearer than most that its number describes performance, not a ruler measurement. Whether that clarity survives the marketing cycle remains to be seen.