IBM has taped out the industry's first test chip built on a sub-1nm fabrication process, using a transistor architecture it calls nanostack.
The 0.7nm-class (7 angstrom) process builds n-type and p-type transistors on separate wafers, then bonds them together using ultra-thin dielectric layers. That vertical stacking, rather than the conventional side-by-side layout, is what lets IBM claim roughly double the transistor density of its 2021 nanosheet gate-all-around node. The company says the process delivers up to 50% higher performance and 70% better energy efficiency versus that 2nm-class baseline, along with a 40% improvement in SRAM density.
The density gains matter most. Squeezing more logic and memory into less space is the hardest problem in advanced chip manufacturing right now, and IBM's approach sidesteps the usual planar shrink by going vertical instead. The catch is real: two advanced wafers must bond with near-perfect alignment, heat dissipation gets harder when an active layer sits farther from the heat sink, and building two separate front-end wafers is expensive. IBM says nothing about cost or yield in its announcement, and the test chip is roughly fingernail-sized — far from the reticle-scale dies that data center AI accelerators require.
This is research-lab work, not a production roadmap. IBM's 2nm process was licensed by Rapidus, which has yet to ship a competitive high-volume chip based on it. Nanostack faces the same gap between Albany demonstration and commercial fab line — IBM estimates five years to mass production, if it gets there at all.