Nagare Labs, a Georgia Tech spinout backed by former Intel CEO Pat Gelsinger, says it can build memory that is nearly as fast as SRAM and nearly as dense as DRAM, layered directly on top of an AI accelerator.
SRAM is the fast but bulky memory built into a processor. DRAM is denser and slower, and usually sits off to the side. Nagare's Z2RAM cell uses two transistors and a shield layer, with no capacitor. For Gen 1, the company projects 5x the density of 2nm SRAM with six stacked layers, 14x the speed of DRAM, and 3x less read energy than SRAM. Those are the company's own projections, not measurements. Nagare also declined to share measured retention, latency, or energy figures.
The measured evidence comes from the founders' academic papers. A three-transistor "boosted" cell held data for more than 300 seconds at 85 degrees Celsius, against 100 milliseconds for a conventional three-transistor design. The catch is that DRAM must stay at or below roughly 95 degrees, and no published cell has shown retention above that line. The cell is also not the two-transistor, single-shield product Nagare is selling.
The timing is the pitch. Stacking DRAM on a processor traps heat, which is why Samsung's zHBM is planned at only about four layers. Stacking SRAM is faster but costs more per bit. Nagare's answer is to deposit all the layers on the chip and pattern them in a single lithography exposure, on standard DUV tools, without EUV. Founder Suman Datta said the work is still lab prototypes, with sampling targeted within four years and shipments within a decade. That single-exposure claim is the one to watch. Academic simulations show returns fading past seven or eight tiers because masks scale with layers, and nothing published yet shows Nagare avoiding that.
The company has a $5 million round led by Playground Global, where Gelsinger is a general partner, and no fab. It is looking for an R&D partner. Co-founder Shimeng Yu said no standard exists for connecting this kind of memory to an accelerator, so Nagare may have to write the interface itself.
There is precedent for caution. Innovative Silicon's capacitorless Z-RAM promised a similar 5x density gain 20 years ago, and AMD licensed it before dropping it. AMD's 3D V-Cache, which stacks cache memory on compute, is the shipping model Datta points to for working with chipmakers.