Researchers have packed and hardened neural network weights for edge chips, cutting memory use by up to 62 percent without giving up much accuracy.
The method, called REQAP, starts with sensitivity-driven mixed-precision quantization: it assigns each layer a bit-width based on how much accuracy that layer can afford to lose, while keeping weights and activations at matching precision. A register-level packing scheme then crams multiple operand pairs into fixed-width register words, so systolic-array accelerators can process several values per instruction (a SIMD-within-a-register trick) instead of one at a time. To guard against hardware faults, common in dense, power-constrained edge silicon, the scheme also copies the most significant bits of sensitive layers into leftover register space, giving triple-redundancy-style protection at minimal cost. Tested in simulation on AlexNet, VGG-11, and ResNet-18, it cut memory use by as much as 62 percent and multiply-accumulate operations by up to 56 percent, while holding up better under simulated faults than both an unprotected baseline and a fully protected model.
Edge accelerators, the chips inside cameras, sensors, and other unattended devices, have to compress models aggressively just to fit them, and that compression usually makes the hardware more fragile when a bit flips from heat, radiation, or aging silicon. This work suggests engineers do not have to choose between a smaller model and a reliable one: the same packing trick that saves memory also frees up space for redundancy.
The catch is that the results are simulated on three now-elderly architectures, AlexNet dates to 2012, so this is still a lab result. The real test is whether accelerator vendors wire it into actual silicon instead of just shipping more memory to paper over the fragility.