The three companies that build the software behind nearly every modern chip now say their AI agents can verify and debug designs dozens of times faster than human engineers.
Cadence, Synopsys, and Siemens EDA each released upgraded AI agents in 2026 for electronic design automation, the software that turns a chip specification into a manufacturable layout. Cadence says its ChipStack agent hit what it calls "bounded Level 5" autonomy in a June demo at Computex, while most of its tech still sits at "advanced Level 4." Synopsys claims its agentic workflow validates RTL code up to 50 times faster than its own non-agentic tools, with a 20% coverage bump. Siemens' Questa One toolkit splits the job across five agents, covering RTL coding, linting, and debugging, and plugs into tools like Claude Code and Cursor.
The autonomy ladders each company touts sound like shared engineering benchmarks, but they are not. Every vendor measures its own agents against its own prior workflow, with no independent evaluator and no standard test suite. The gains cluster almost entirely in front-end verification, which is already code-like and well suited to language models, while physical layout work, limited by compute-heavy simulation and unforgiving physics, has barely budged.
Smaller rival Empyrean claims its own agent cut a layout task from four weeks to one. Different company, same move: let the vendor grade its own homework and call it a benchmark.