A new inference-time framework lets a frozen large language model generate and repair printed circuit board schematics without any hand-labeled test oracles.
Researchers introduced PCBSchemaGen, a training-free system that wraps an off-the-shelf LLM with three components: a domain schema derived from IC datasheets, a deterministic five-layer verifier that scores candidates and pinpoints pin-level errors, and a Thompson Sampling bandit that selects which candidate to refine next. The key constraint the team worked around is that PCB schematic design has no unit-test equivalent — correctness depends on physical constraints tied to real component packages, not a function that returns pass or fail. Tested across 227 tasks spanning 22 circuit domains, the open-weight Gemma-4-31B model passed 81.3% of PCBBench tasks under the framework. A prompting-only baseline on the same model collapsed on complex system-level designs.
The result matters because it sketches a path for applying LLMs to engineering domains where ground-truth oracles simply do not exist. Most code-synthesis benchmarks are built around unit tests; PCB design, like many physical-world engineering tasks, is not, and that gap has kept LLM tooling on the sidelines.
The framework and benchmarks are open-sourced, which at least makes the claims checkable — though translating an 81% pass rate on benchmark tasks into a tool a hardware engineer would trust in production is a longer road than the paper covers.