AI is no longer just fine-tuning chip layouts. It is writing RTL, running verification loops, and in some cases proposing architectural choices, shrinking the human role in chip design with each new generation of tools.
For years, EDA vendors like Cadence, Synopsys, and Siemens EDA have sold machine-learning and reinforcement-learning tools that optimize placement, routing, and power-performance-area tradeoffs on designs engineers already defined. Google's AlphaChip pushed further, using reinforcement learning for floorplanning across three generations of TPUs. Nvidia goes deeper still, training models on its own proprietary RTL to automate engineering tasks a merchant EDA vendor could never touch. OpenAI's Jalapeno chip is the clearest real-world case so far: AI handled implementation, verification, and arithmetic-circuit optimization, cutting the design-to-tapeout timeline to nine months and improving a BF16 multiplier by 56% and an FP4 dot-product block by 21% over human baselines.
The real story is the gradient, not any single headline. Architect Labs says its Redwood accelerator had its RTL, verification, and firmware generated almost entirely by AI from a two-person spec in under two weeks. But it has never been taped out, and its 3.4x performance-per-watt claim over Nvidia's Jetson Orin Nano rests on a projected design, not silicon that exists. OpenAI's numbers, by contrast, come from a chip that actually shipped.
Humans still decide what a chip is supposed to do. AI is just getting faster at turning that decision into transistors, and eventually those transistors will help train the AI that designs the next batch.