AI agents write better chip designs when they stop coding straight to RTL and think one abstraction level up first.
A new study pits four chip-design workflows for large language model agents against each other on FPGAs: writing RTL directly, using an agent to generate high-level synthesis (HLS) code, refining RTL after it's compiled from HLS, and refining RTL directly without ever touching HLS. The researchers then combined the two best-performing steps into a workflow called AHRR (Agent-based HLS with RTL Refinement), where an agent designs in HLS and a second pass tunes the resulting RTL. Across an 11-task benchmark suite, AHRR beat Direct RTL Design by 2.6x on a geometric-mean speedup basis. The team used FPGAs because they're cheap to deploy and iterate on, though they argue the tradeoffs they found should carry over to other chip targets.
The result suggests the bottleneck in agentic chip design isn't the model's reasoning, it's the abstraction it's forced to reason in. HLS hands agents pre-packaged design patterns to draw on, while a later RTL pass claws back the low-level optimizations that get lost in translation. That's a useful data point beyond chips too: for AI coding agents generally, picking the right intermediate representation can matter as much as picking a smarter model.
One catch: the paper measures how fast the resulting circuit runs, not how long or how expensive it is for the agent to get there, so whether AHRR is actually cheaper end-to-end is still an open question.