AI agents are now writing scripts, invoking tools, and passing design files between stages in chip development pipelines — and a new survey argues the field needs ground rules before things go wrong.
Researchers reviewed 82 systems that use large language models inside electronic design automation workflows and organized them into three categories: systems that stay within a single design stage, systems that carry state across multiple tools and sessions, and systems that cross organizational or knowledge boundaries. The central concern isn't whether the AI can complete a task, but whether what it hands off to the next stage is actually valid — meaning it meets the downstream consumer's requirements and carries enough context to be trusted. The paper proposes a five-layer communication protocol, called EACP, covering how agents discover each other, format messages, invoke tools, orchestrate workflows, and handle security and IP constraints.
Chip design is one of the few engineering domains where a single missed assumption between pipeline stages can cost months and millions of dollars in respins. Formalizing what a "valid handoff" means — before LLM agents are embedded deeper into production flows at companies like Synopsys, Cadence, or their customers — is exactly the kind of infrastructure work the field needs and rarely gets ahead of the adoption curve.
The survey is framed as a research agenda, not a shipping standard, which means the gap between this vocabulary and an actual interoperability spec remains wide open.