AI can write software, but chip designers still don't trust it to write hardware — a new framework aims to change that.
Researchers have proposed a system that combines large language models with formal verification methods to generate register-transfer level (RTL) code, the low-level hardware description language used to design chips. Rather than asking an LLM to produce a finished design in one shot, the framework applies a defined set of transformation rules iteratively, letting an agent step through a specification and arrive at RTL output with mathematically guaranteed correctness. The paper reports the approach is both effective and efficient in experiments, though independent benchmarks against existing tools are not yet available.
The stakes here are higher than in software. A bug in production code ships a patch; a bug baked into a chip design costs millions in re-spins and months of lost time. That asymmetry explains why hardware teams have been far slower to adopt AI assistance than software teams, even as LLM coding tools have become routine. A framework that wraps LLM output in formal guarantees could lower that barrier meaningfully.
The catch is that formal methods are only as good as the rules they enforce — if the transformation set has gaps, the guarantee has gaps too. The research is at the preprint stage, so the chip industry's notoriously cautious toolchain vendors will want a lot more stress-testing before any of this gets near a tape-out.